Path-constrained and incremental floorplanning using sequence pairs

Author

Cheng Chang Yu

Date of Award

5-2000

Degree Type

Thesis

Degree Name

Master of Science

Major

Computer Science

Major Professor

Dinesh Mehta

Committee Members

Bruce Bomar

Abstract

This research focuses on the floorplanning stage of the VLSI physical design cycle. The first part of this research is on path-constrained floorplan. In order to maximize CPU performance and improve clock cycle time, modules on critical paths must be placed in a straight line from an input pin to an output pin. This technique uses the sequence-pairs method. The second part of this research is on incremental floorplan. Given a floorplan, we want to generate a different floorplan that is very similar to the original floorplan after incremented changes in module sizes have been made. Once again, we use sequence-pairs with various cost functions to solve the problem. We have been successful in obtaining a provably correct solution for a limited version of the path-constrained problem. Experimental results demonstrating the efficiency of our methods are also presented.

Recommended Citation

Yu, Cheng Chang, "Path-constrained and incremental floorplanning using sequence pairs. " Master's Thesis, University of Tennessee, 2000.
https://trace.tennessee.edu/utk_gradthes/9538