Masters Theses
Date of Award
12-1996
Degree Type
Thesis
Degree Name
Master of Science
Major
Electrical Engineering
Major Professor
Bruce W. Bomar
Committee Members
L. Montgomery Smith, Roy D. Joseph
Abstract
This thesis presents the development of a circuit board which converts the bidirectional bit-parallel communications port data bus of the Texas Instruments TMS320C4x family of digital signal processors into a high speed bit-serial data bus. The usual method of interconnecting Texas Instruments TMS320C4x digital signal processors is by ribbon cables connected to parallel communications ports. The cables are cumbersome and do not allow reliable data communications over distances greater than one meter. The board overcomes this limitation by using a Cypress CY7B923 Hotlink transmitter to convert from eight bit parallel to ten bits serial using an internal 8B/10B data encoder. The transmitter sends the data at bit rates from 160 to 330 megabits per second either through a category-5 unshielded twisted pair cable or through multimode fiber optics. A Cypress CY7B933 Hotlink receiver decodes and converts the data from ten bit serial back to eight bit parallel. The maximum length for a category-5 cable connected to the Hotlink transmitter/receiver pair is 150 feet at a serial data rate of 250 megabits/second. The board uses three state machines compiled into an Altera EPM7129ELC84-15 programmable logic device. One state machine is responsible for communicating with and transferring data to the TMS320C4x digital signal processor. Another state machine is responsible for transmitter control and data transmission. The last state machine controls the receiver. Each of the state machines was implemented using VHDL hardware description language in the Altera Max Plus II development environment. The TMS320C4x communications board has been built and its capabilities tested. The board has allowed a TMS320C40 processor to send data across a 15 foot category-5 unshielded twisted pair cable at 4.9 megabytes per second. This data rate should be the same using a 150 foot cable. Two suggestions are made for improving the data rate. First, the speed at which the state machines are operating can be improved by compiling the VHDL code into a faster programmable logic device. Second, the ‘C4x interface can more quickly detect an attempted read to or write from a TMS320C4x processor if the synchronization flip flops used by the 'C4x state machine are removed.
Recommended Citation
Leugers, Robert Earl, "The development of a TMS320C4x serial communications board. " Master's Thesis, University of Tennessee, 1996.
https://trace.tennessee.edu/utk_gradthes/10885