Masters Theses

Quinn Devine

Date of Award

5-1996

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Donald W. Bouldin

Abstract

The design of application specific integrated circuits is becoming more complex as technology improves, allowing higher circuit density and faster speeds. As the system complexity increases, so does the complexity of the design and physical implementation processes. Consideration must be made of the higher probability of errors in the fabrication of a very large device. A system can be designed so as to allow one to detect manufacturing faults after it has been fabricated, therefore, faulty parts can be detected before they are shipped, which reduces per part cost significantly. Consideration of other system configurations might be necessary to further reduce costs. A single, large chip design may be partitioned into a configuration of several die on a Multi-Chip Module, which reduces the cost of the system with respect to the monolithic version. Further cost reductions can be had if a different method of bonding the chip I/O to the MCM substrate is implemented. A tradeoff must occur between different partitions that considers the relative cost and performance, in order to determine the best solution. A very large design (SPARC CPU) is synthesized and physically imple-mented as a single chip and as an MCM with wire bond die. The per part cost of the system is determined to be $529.50 and $303.13 for the single chip and MCM, respectively. However, the MCM is about 3.7 times larger than the monom-lithic version. The cost of an MCM with area array bonded die is estimated to be $54.38 and is only about 10% larger than the monolithic version. These cost savings should convince a system designer to consider an MCM implementation of a very large design, as opposed to a die in a single chip package.

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