Masters Theses

Date of Award

12-1998

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Donald W. Bouldin

Committee Members

Paul Crilly, Miljko Bobrek

Abstract

System level simulation and verification help in obtaining information necessary to evaluate and verify new designs and implementations. The use of behavioral modeling helps in obtaining these results with minimal simulation time and resources. Use of the simulation data can provide guidance during prototype production and debugging. The creation and capabilities of a behavioral model for a GHz transmitter and receiver chips are presented. The working of the model under different link configurations was also verified. The models were tested with a mode bit set for both the 16-bit and 20-bit parallel words. The methodology for importing FPGA designs from the Foundation Series to ViewLogic environment for board level simulation is also presented. The Xilinx FPGA designs, ALM FPGA and Heap Manager FPGA, were successfully imported into the ViewLogic Powerview (v6.0) CAD tool with post-layout timing information included in the netlist. The Heap manager FPGA was tested in the Foundation Series simulator. The design achieved its performance requirements of a minimum of 40MHz working frequency. The steps towards creating a mixed signal simulation model are also explored by simulating an analog behavior model.

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