Masters Theses

Date of Award

5-1999

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Bruce Bomar

Committee Members

Roy S. Joseph, L. Montgomery Smith

Abstract

The development of a Texas instruments Module (TIM) compliant Digital SignalProcessor (DSP) module, using the Texas Instruments TMS320C6201 (C6201) DSP, is presented. Currently, DSP modules based on the Texas Instruments TMS320C4x(C4x) family of DSPs are widely used for message passing multiprocessing DSPapplications such as real-time processing of data and image processing. The Interconnection of the TIM-compliant C4x DSP modules is accomplished using motherboards based on standard bus types, such as VME or PCI, and communication ports (comm ports) built into the C4x DSP. The purpose of the work described in this thesis was to provide a TIM-compliant DSP module with the improved computational performance of the C6x family of DSPs, which would also be compatible with theexisting VME or PCI bus motherboards.One drawback to using the C6201 DSPs in this application is the lack of C4xtype communication ports (comm ports) in these new DSPs. In order for the C6201 TIM to be compatible with the existing motherboards, it must provide C4x- compatible commport functionality. An FPGA was used to convert the C6x host port into multiple C4x compatible communication ports and to provide the potential for future co-processinghardware.The major effort of this development was the designing, building and testing of the C6x module hardware and the C4x-compatible comm port interface implemented in FPGA. The first phase of this design involved the hardware architecture; this consisted of the selection of components needed to fulfill the design constraints, and the design of the module printed circuit board (PCB). The major components of this DSPmodule consist of theC6201 DSP. The external ai memory devices, and an Altera PF10 10pA Field Programmable Gate Array (FPGA). The memory devices include 4MB of SDRAM. 256kB of SBSRAM, and a 512kB Flash ROM for storing boot code. The Second phase of this design dealt with the host port to comm port conversion hardware implemented in the FPGA. The C6x host port was used to exchange data and control information with the FPGA. This hardware was developed in the VHDL hardware description language and graphic design files using Altera MAX+PLUS II software.The C6201 DSP module has been built and tested. The board successfully executed both read and write transfers with another motherboard using the C4x compatible communication port interface. The data exchange was across a 2.5' ribbon cable at an average read transfer data rate of 7.18 Mbytes/S and an average write transfer data rate of 5.15 Mbytes/S.

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