Development of a TIM module for data buffering and reconfigurable computing

Author

Brannon Paul Wells

Date of Award

8-2000

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Bruce Bomar

Committee Members

Roy S. Joseph, L. Montgomery Smith

Abstract

The development of a Texas Instruments Module (TIM) compliant memory module is presented The module acts as a high-speed buffer for data acquired from an A/D TIM moduleand can also be used for reconfigurable computing applications The module provides 256 Mbytes of SDRAM memory(256 times the memory available on current TIM modules with similar functionality), and uses the Altera APEX 20K and FLEX 10KE Programmable Logic Devices (PLDs) for all control operations

The development of the memory module was divided into two parts,the hardware designed the software design The hardware design includes requirements capture, functional description and schematic design,and PCB layout The software design covers the development of the SDRAM controller implemented in the APEX 20K and the communications interface implemented in the FLEX 10KE, which includes the definition of a custom method for 16-bit data transfer between the A/D TIM module and the memory module.

The memory module has been constructed, configured, and tested. The module is capable of storing up to 256 Mbytes of data from an A/D TIM module at a rate of up to 116 Mbytes/sec,and is able to transfer all of the stored data to a PC via the TIM-40 PCI Motherboard to which It and the A/D TIM module are mounted.

Recommended Citation

Wells, Brannon Paul, "Development of a TIM module for data buffering and reconfigurable computing. " Master's Thesis, University of Tennessee, 2000.
https://trace.tennessee.edu/utk_gradthes/9528