Masters Theses

Date of Award

5-2020

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Daniel Costinett

Committee Members

Hua Bai, Leon Tolbert

Abstract

Mobile devices and other portable electronics require fast and efficient battery charging to meet the growing energy demands of modern technology. Charging time is reduced with higher charging current, but the current is limited by allowable on-chip power losses specified by thermal constraints for small area integrated circuits (ICs). As compared to a single-cell battery system requiring a given charging time, a two-battery series-connected (2S) cell configuration increases the overall voltage and thus reduces the necessary charging current to achieve the same charging time. Today, commercially available 2S battery chargers on the market currently consist of multi-chip solutions that manage charging, battery cell balancing, battery protection, and modulation control. Those chargers tend to be bulky because of multiple, independent ICs. In this work, a switched capacitor (SC) three-level boost converter is proposed as a single-chip integrated solution to provide simultaneous charging and active balancing for 2S battery topologies. The proposed charging circuit adopts the balancing functionality inherent to switched capacitor converter (SCC) techniques with two additional low-power transistors. Converter evaluation is performed across various input voltages, charging currents, and asymmetric battery voltages. The criteria for each operating scenario is a maximum on-chip loss of 1 W, 5-20 V range at the input, and up to 6.4 A charging current. State space modeling including converter parasitics developed for simulation analysis, and a hardware prototype built using GaN FETs enabled validation of the converter models. A proposed strategy for integration is also addressed as the converter’s charging and balancing capabilities are designed to meet or exceed the current market standard.

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