Masters Theses

Date of Award

12-2018

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Daniel Costinett

Committee Members

Benjamin J. Blalock, Syed K. Islam, Leon M. Tolbert

Abstract

By 2020 it is predicted that 1/3 of all data will pass through the cloud. With society's growing dependency on data, it is vital that data centers, the cloud's physical house of content, operate with optimal energy performance to reduce operating costs.Unfortunately, today's data centers are inefficient, both economically and environmentally. This has led to an increase in demand for energy-efficient servers. One opportunity for improved efficiency is in the power delivery architecture which delivers power from the grid to the motherboard. In this dissertation, the main focus is the intermediate bus converter (IBC), used for the intermediate conversion, typically 48-12V/5V, in server power supplies. The IBC requires compact design so that it can be placed as close to the load as possible to enable more space for computing power and high efficiency to reduce the need for external cooling. Most commonly used converter topologies today include expensive bulky magnetics hindering the converter's power density. Furthermore, high output current of an IBC makes the efficiency very sensitive to any resistance, such as magnetic parasitic resistance or PCB trace resistance. In this work, analytical loss models are used to review the advantages and disadvantages of frequently used IBC topologies such as the phase-shifted full bridge and LLC. The Hybrid Dickson Switched Capacitor (HDSC) topology is also analyzed. The HDSC's high step-down conversion ratio and low dependence on magnetics due to the reduced applied volt-seconds, provides a new opportunity for applications such as the intermediate bus converter. The HDSC designs the on-time of devices in order to achieve soft-charging between flying capacitors. Other advantages of the HDSC include low switch stress, small magnetics and adjustable duty cycle for voltage regulation. Challenges, such as minimizing parasitic inductance and resistance between flying capacitors, are addressed and recommendations for PCB layout are provided. In this paper, a 4:1 24-5V and 8:1 48-5V, 100W GaN-based HDSC is designed and tested. The influences of capacitor mismatch and limitations placed on soft-charging operation for the HDSC is also modeled. This analysis can be used as a tool for designers when selecting flying capacitors.

Download
Files over 3MB may be slow to open. For best results, right-click and select "save as..."

Share

COinS