Sparse Matrix Sparse Vector Multiplication using Parallel and Reconfigurable Computing

Author

Kirk Andrew Baugher, University of Tennessee

Date of Award

5-2004

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Gregory D. Peterson

Committee Members

Donald W. Bouldin, Kwai L. Wong

Abstract

The purpose of this thesis is to provide analysis and insight into the implementation of sparse matrix sparse vector multiplication on a reconfigurable parallel computing platform. Common implementations of sparse matrix sparse vector multiplication are completed by unary processors or parallel platforms today. Unary processor implementations are limited by their sequential solution of the problem while parallel implementations suffer from communication delays and load balancing issues when preprocessing techniques are not used or unavailable. By exploiting the deficiencies in sparse matrix sparse vector multiplication on a typical unary processor as a strength of parallelism on a Field Programmable Gate Array (FPGA), the potential performance improvements and tradeoffs for shifting the operation to hardware assisted implementation will be evaluated. This will simply be accomplished through multiple collaborating processes designed on an FPGA.

Recommended Citation

Baugher, Kirk Andrew, "Sparse Matrix Sparse Vector Multiplication using Parallel and Reconfigurable Computing. " Master's Thesis, University of Tennessee, 2004.
https://trace.tennessee.edu/utk_gradthes/4651