Masters Theses

Date of Award

8-2002

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Syed K. Islam

Committee Members

Benjamin J. Blalock, Donald W. Bouldin

Abstract

Timing jitter in clock signals presents a limitation to the performance of a variety of applications and systems. The criticality of the issue is discussed with the A-D converter as the backdrop. Timing errors in the sampling clock, the analog input signal and the aperture uncertainty of the A-D converter degrade the signal-to-noise ratio performance. In this thesis, a method to estimate the aperture uncertainty of the converter has been developed. The model accounts for the converter’s quantization noise and differential non-linearity errors and thereby improves the accuracy of the estimation. The technique was applied to a 10-Bit converter and the results are presented.

For clock generation using PLLs, ring oscillators are attractive from an integration and cost point of view for use as a VCO. Their timing jitter can be improved by increasing the output voltage swing, the gate overdrive of the transistors of the differential pair and the power dissipation while maintaining just a minimum required small signal gain for the delay stage. In this thesis, it is shown that the maximum possible output voltage swing is dependent entirely on technology parameters. The proposed oscillator topology uses an n- MOS differential pair with a class of load elements called the ‘symmetric loads’ and is designed for the maximum possible output voltage swing. Frequency variation is achieved by driving the body of the symmetric loads in order to keep the swing and hence phase noise constant across frequencies. Also, the frequency vs. body voltage characteristics has been derived and found to be linear. Finally, the proposed theoretical predictions have been validated with simulation results.

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