Masters Theses

Date of Award

12-2002

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Bruce W. Bomar

Committee Members

Roy D. Joseph, L. Montgomery Smith

Abstract

In this study, a simple dc-balanced encoding scheme was developed to reduce the bit error rate for high-speed data transmission over CAT-5 cable using Low-voltage Differential Signaling (LVDS). The dc balance encoder was implemented to make binary sequences with a spectral null at zero. A data transmission controller using the dc balanced scheme was implemented in an Altera Field Programmable Gate Array (FPGA), including data generators that send data to a DS92LV1023 10-bit bus LVDS serializer, data checkers for checking the data coming from a DS92LV1224 10-bit bus LVDS deserializer, and dc balance and non-dc balance encoders. Data was transmitted over various lengths of CAT-5 cable with and without dc balance to determine the effect of the dc balance scheme on transmission errors.

To generalize the type of data used in the transmission tests, three different kinds were selected for the error testing: pseudo-random numbers generated by a 32-bit Linear Feedback Shift Register (LFSR) binary polynomial generator; consecutive numbers generated by a counter; and data looked-up from a Read Only Memory (ROM) implemented in an FPGA embedded memory block.

The data transmission controller was constructed, configured, and tested both with and without dc balance. It provides a data transmission rate of 538.8 Mbps, and is able to send the number of errors encountered during the transmission process to a PC via the PCI bus. Testing results verify that the dc balance scheme adopted in this thesis significantly improves the accuracy of the serial data transmission. Both dc-balanced and non-dc-balanced encoding proved error-free out to cable lengths of about 19.8 meters. DC-balanced encoding also extended the error-free cable length by about 1.5 meters and reduced errors by about 60% for longer cables.

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