Masters Theses

Date of Award

5-2004

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Dr. Benjamin J. Blalock

Committee Members

Dr. Syed K. Islam, Dr. M. N. Ericson

Abstract

A precise and stable voltage reference is essential to analog/mixed-signal SoC (system-on-a-chip) applications. The most commonly used voltage reference in standard CMOS processes, the bandgap voltage reference, is limited due to output drift in wide temperature range applications. The temperature drift associated with the bandgap voltage reference is non-linear, thus temperature compensation is difficult. A new reference circuit, the JFET-based voltage reference, is proven to be more temperature stable. However, the JFET-based voltage reference requires a specialized Bi-CMOS process with additional fabrication steps to alter the channel doping for selected devices. The purpose of this thesis is to investigate the feasibility of the JFET-based voltage reference circuit topology in a CMOS-compatible process. The novel G4-FET device fabricated on a standard PDSOI (partially-depleted silicon-on-insulator) CMOS process is chosen as an alternative to the JFET device. A theoretical development of the G4-FET is summarized and results of device characterization are presented. Based on device characterization, all four gates of the G4-FET device are exploited to achieve an equivalent circuit operation without requiring any additional process steps. Results from this characterization are used to design an improved voltage reference based on G4-FETs and test results from a prototype reference circuit are shown including output temperature coefficient, output noise, and power supply rejection. The output voltage achieves approximately constant output variation with temperature over the temperature range of −5 °C to 85 °C, implying that the circuit may be readily temperature compensated, in this case by an inverse-PTAT (proportional-to-absolute-temperature) current. Finally, suggestions for improved reference performance and fully monolithic compatibility are given.

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