Masters Theses

Date of Award

6-1984

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

James C. Hung

Committee Members

J. M. Bailey, Donald W. Bouldin

Abstract

The applicability of a hardware efficient realization of the distributed arithmetic approach for implementing digital filters was the concern of this study. To this end, 2 sixth order Butterworth filters were implemented. The first had a cutoff frequency that was 20% of the Nyquist frequency while the second had a cutoff frequency that was 2% of the Nyquist frequency. Each filter was implemented as 3 cascaded second order sections. The output roundoff error of the filters was reduced by choosing coefficients for each second order section so that the noise due to that section was minimum. Ordering of the cascaded sections was also chosen to reduce the output roundoff error. The procedures for defining filter coefficients and ordering the second order sections are presented and applied to the implemented filters.

The resulting filters were evaluated and shown to accurately reproduce the desired transfer function. The cost of the 20% implementation was compared to that of 3 alternative implementations. The distributed arithmetic approach proved cheaper than the other alternatives. In addition, the output roundoff error of the implemented filters was estimated and found to be 29 times less than the output roundoff error of a comparable minimum multiplier filter. Thus, the implemented filters were concluded to be a cost effective implementation of reduced roundoff error filters.

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