Masters Theses

Date of Award

6-1985

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Bruce W. Bomar

Committee Members

Roy Joseph, Dennis Keefer

Abstract

Many of the low roundoff noise digital filter structures which have been proposed in recent years are compared with respect to their efficiency when executed on a common digital signal processor architecture. The architecture used is the modified Harvard architecture on which the Texas Instruments TMS32010 integrated circuit is based. The various state-space and state decimation structures, as well as the wave digital filter structure derived from a passive LC analog filter are compared. Closed-form expressions are developed for the maximum sample rate attainable with each structure as a function of filter order. These equations, together with the roundoff noise gain, serve as criteria for selecting the structure most suitable for a particular application.

Results indicate that the state-space structures execute much more efficiently on the reference architecture than does the wave digital filter. A technique for relaxing the scaling constraints on state-space structures to further improve execution efficiency is also proposed. With this technique it is possible to obtain a nondecimated state-space realization of a sixth-order filter which will operate at sample rates up to 96 kHz on the TMS32010. With state decimation this increases to over 123 kHz.

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