Masters Theses

Robert Chavez

Date of Award

12-1985

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Robert E. Bodenheimer

Committee Members

R. W. Rochelle, J. M. Bailey

Abstract

In the past decade, various techniques and strategies have been introduced by a number of leading designers for controlling the operation of one or more Arithmetic Processing Units, coprocessors, in a system which share common address lines, data lines, and main memory with a central processor. Specifically, techniques and strategies as applied to some commercially available and some non-available Floating Point Processors which utilize either an 8-bit, 16-bit, or 32-bit architecture are reviewed. A comparative analysis of the performance of these devices is then presented to determine the more desirable features of each leading to a recommendation pertaining to the future design of communications systems for Arithmetic Processing Units.

Download
Files over 3MB may be slow to open. For best results, right-click and select "save as..."

Share

COinS