An investigation of gate level design automation and global routing in VLSI design

Author

Suresh Rajgopal

Date of Award

8-1987

Degree Type

Thesis

Degree Name

Master of Science

Major

Computer Science

Major Professor

J. R. B. Cockett

Committee Members

Jean R. S. Blair, David Straight

Abstract

This thesis deals with design automation at the logic gate level and practical global routing algorithms for VLSI design. An approach to performing automated design at the logic gate level is outlined. To verify this approach, an experimental sys tem was set up on an IBM-PC/AT, in an environment compatible with VIVID, an available integrated design system. Gate level design was performed, and circuit descriptions were generated in the ABCD language of the VIVID system. During the course of the design, VLSI routing algorithms were explored in the design environment and a near optimal algorithm to perform two-terminal global routing was designed and implemented.

Recommended Citation

Rajgopal, Suresh, "An investigation of gate level design automation and global routing in VLSI design. " Master's Thesis, University of Tennessee, 1987.
https://trace.tennessee.edu/utk_gradthes/13562