Masters Theses

Date of Award

12-1987

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Donald W. Bouldin

Committee Members

Robert W. Rochelle, Robert E. Bodenheimer

Abstract

A parallel processor for high-speed execution of the OPS5 Expert System language was designed and implemented at the Oak Ridge National Laboratory. The parallel architecture is presented along with the initial implementation of this architecture.

OPS5 is a popular rule-based Expert System language that is currently used in many fields. A brief description of the language will be given to introduce the parallel Network Architecture. This architecture includes a transmit-only bus from the Host system to any number of parallel Rule Processors (RPs). This transmit-only bus is implemented by a unique memory-mapped method that allows the Rule Processors to be decoded in parallel for a memory write by the Host system.

The initial implementation consists of 64 parallel Rule Processors and is based on the Motorola MC68000 microprocessor. A custom board was designed that contains four MC68000S, each with 512 kbytes of memory. These parallel processors are controlled by a single Host system, which is a conventional Multibus 68000 computer. This control is through a single Interface Board which minimizes replication of control and addressing logic.

The software for this system is mentioned briefly in an overview of the implementation of OPS5 into the Network Architecture. The software description is intended only to give some background to the implementation of the OPS5 language.

Results of the design and implementation are discussed along with ideas for possible future extensions using the parallel Network Architecture.

A patent application has been filed pertaining to this Network Architecture and to its first hardware implementation.

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