Masters Theses

Date of Award

12-1988

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

D. W. Bouldin

Committee Members

Robert Bodenheimer

Abstract

An intelligent quad video frame buffer module was designed, developed and tested for use as the main image storage and processing element of a commercially available image processing system. Through the use of dynamic Video RAM and programmable gate arrays, the module allowed the system cost, physical size and power consumption to be reduced by nearly a factor of four.

The two-mega bytes of memory were organized as four independent image tiles to store four 512 by 512 by 16-bit images, or eight 512 by 512 by 8-bit images. The image tiles were designed to function independent of one another and to allow for up to sixty-four tiles to be combined in a system to form up to a 4096 by 4096 image.

Video RAM was utilized as the image storage media as an economical method of reading the pixel data from the image airay at thirty frames-per-second to maintain the raster-scan display of the system. In order to simultaneously read pixel data at video rates from the memory array for image display and to write pixel data to the memory array for image capture, a parallel bank architecture was developed to boost the bandwidth of the random port of the Video RAM to allow image writes via the random port while the serial port was designed to be utilized for the video reads. The video address generation for the reading and the writing of the pixel data was designed to perform pixel replication, for image zoom, and an image origin offset, for image scroll.

To accelerate the execution of image processing algorithms in the system, a highperformance digital signal processor was included in the design. The high memory to processor bandwidth coupled with the high instruction rate of the processor, significantly reduced the execution times of image processing routines compared to their execution times from an external processor. Several image memory paging techniques were developed to compensate for the limited address space of the processor.

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