Masters Theses

Date of Award

12-1988

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

B. W. Bomar

Committee Members

Roy Joseph, Alfonso Pujol

Abstract

The capability to acquire and reduce focal plane array (FPA) data in real time is a critical requirement to FPA testing. The initial data system developed at the AEDC for this application used buffer memory modules located in a Digital Equipment Corporation (DEC) computer system to acquire and store the raw FPA data. This system, though inexpensive, created a "processing bottleneck" since all of the data reduction was performed by a single LSI-11/73.

The initial data system was improved in throughput capability and overall system performance by the development of a parallel signal processing system which distributes the FPA data reduction task over several digital signal processors. The development of a digital signal processor which has the capability to acquire and reduce data from two FPA data channels in real time is presented. These boards maintain the DEC system interface and provide both input data buffering from the FPA and processed data buffering to the DEC computer. The ability to process data in real time is provided by a high speed fixed point integer signal processor. The signal processor maintains high computational accuracy since many of the noise computations require processing of very small numbers A test to verify proper FPA processing was developed and used to successfully check the signal processor. In addition, the signal processing software was benchmarked to verify real time operation.

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