Masters Theses
Date of Award
8-2012
Degree Type
Thesis
Degree Name
Master of Science
Major
Computer Engineering
Major Professor
Gregory D. Peterson
Committee Members
Gregory D. Peterson, Hairong Qi, Nathanael Paul
Abstract
As designers and researchers strive to achieve higher performance, field-programmable gate arrays (FPGAs) become an increasingly attractive solution. As coprocessors, FPGAs can provide application specific acceleration that cannot be matched by modern processors. Most of these applications will make use of large data sets, so achieving acceleration will require a capable interface to this data. The research in this thesis describes the design of a memory controller that is both efficient and flexible for FPGA applications requiring floating point operations. In particular, the benefits of certain design choices are explored, including: scalability, memory caching, and configurable precision. Results are given to prove the controller's effectiveness and to compare various design trade-offs.
Recommended Citation
Hunter, Bryan Jacob, "A Memory Controller for FPGA Applications. " Master's Thesis, University of Tennessee, 2012.
https://trace.tennessee.edu/utk_gradthes/1305