Masters Theses

Date of Award

5-2024

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Himanshu Thapliyal

Committee Members

Nicole McFarlane, Benjamin J. Blalock

Abstract

The Internet of Things (IoT) has become commonplace in society, but it has been demonstrated that many IoT systems are vulnerable to significant security exploits. This necessitates the need for a closer examination of IoT security. IoT design prerequisites are low power consumption and an emphasis on smaller die areas for increased production yield. Security on the software level typically provides adequate protection but there are hardware-level exploits that are difficult or impossible to counteract. Booting attacks, eavesdropping and interference, and Side-Channel Attacks (SCA) are exploits deployed against IoT devices on the hardware level. To combat these vulnerabilities, several lightweight hardware encryption techniques such as PRESENT-80, in particular, are developed for their lower power usage and smaller device footprint. However, studies show that PRESENT-80 is still vulnerable to SCA or power analysis attacks. Literature on improved PRESENT-80 circuits provides SCA resistance but the trade-offs are often an increase in device area and distinguishable power usage patterns.

A recently developed adiabatic circuit technique introduced as Energy Efficient Positive Feedback Adiabatic Logic (EE-SPFAL) shows promise of resistance against SCA and consumes lower power compared to traditional CMOS digital circuits. However, the simulation results are solely presented through the schematic layer without the inclusion of post-layout simulation. This work aims to fill the gap by providing the layout design of EE-SPFAL standard cells and a prototype of 1 Round PRESENT-80 S-box using EE-SPFAL. Post-layout Correlation Power Analysis (CPA) attacks and energy consumption analysis are conducted and compared with the conventional CMOS circuit. In addition, this work aims to show the effects of parasitic capacitance within inter-logic cell routing on SCA resistance and highlight the limitations of schematic-only simulations against CPA attacks. This work is designed using open-source CAD tools from Efabless/Google with Skywater 130nm technology.

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