Masters Theses

Bo Su

Date of Award

12-1998

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Bruce W. Bomar

Committee Members

Roy D. Joseph, Bruce A. Whitehead

Abstract

In this study, the implementation of second-order floating-point IIR filters by FPGAs was investigated. A small word length floating-point representation was chosen to keep the roundoff noise below the input quantization error while also keeping the logic resources required as low as possible. The state-space and direct form structures were compared; the state-space structure was chosen because of its low roundoff noise at the filter output.

A bit-parallel floating-point multiplier used especially for filter design was developed on the base of a megafunction of Altera Company. A bit-serial floating-point multiplier was designed to reduce the logic cells. The logic resources used and speed of computation were investigated with different small floating-point representations.

The second-order state-space floating-point IIR filter was designed using the floating-point multipliers and a floating-point adder megafunction. The results show that floating-point filter design can be implemented in current FPGA with reasonable speed and logic resources. Depending on the number bits of mantissa and exponent, the second-order IIR sample rate can be over 1 MHz if the bit-parallel floating-point multiplier is used. Logic resources can be saved by using bit-serial multiplier, especially for a large number of mantissa bits, but the speed is comparatively low.

Representative implementations were described in VHDL or AHDL and complied and simulated using Altera MAX+PLUS II software.

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