A low dead time variable CMOS delay for the nuclear weapons identification system

Author

Bryan Scott Puckett

Date of Award

8-1998

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

T. V. Blalock

Committee Members

Mike Paulus, Rochelle

Abstract

The architecture and performance of a new CMOS based, low dead time, variable delay is described. This delay was developed to provide capability for channel synchronization in the Nuclear Weapons Identification System (NWIS) front­end electronics ASIC. The delay is variable over a 500ns range in smaller than 100ps steps. Low dead time is achieved by using a switched parallel channel architecture. The delay channels are feedback stabilized using a phase locked loop (PLL) locked to a crystal reference. A prototype has been fabricated in the 1.2u AMI process and tested to evaluate its performance.

Recommended Citation

Puckett, Bryan Scott, "A low dead time variable CMOS delay for the nuclear weapons identification system. " Master's Thesis, University of Tennessee, 1998.
https://trace.tennessee.edu/utk_gradthes/10345