Masters Theses
Date of Award
12-2023
Degree Type
Thesis
Degree Name
Master of Science
Major
Electrical Engineering
Major Professor
Benjamin J. Blalock
Committee Members
Nicole McFarlane, Garrett Rose
Abstract
As CMOS process nodes scale to smaller feature sizes, process optimizations are made to achieve improvements in digital circuit performance, such as increasing speed and memory, while decreasing power consumption. Unfortunately for analog design, these optimizations usually come at the expense of poorer transistor performance, such as reduced small signal output resistance and increased channel length modulation. The ring amplifier has been proposed as a digital solution to the analog scaling problem, by configuring digital inverters to function as analog amplifiers through deadzone biasing. As digital inverters naturally scale, the ring amplifier is a promising area of exploration for analog design. This work presents a ring amplifier scaling study by demonstration of scaling an output capacitor-less, ring amplifier based low-dropout voltage regulator designed in a standard 180 nm CMOS process down to a standard 90 nm CMOS process.
Recommended Citation
Corum, Steven, "A Case Study in CMOS Design Scaling for Analog Applications: The Ringamp LDO. " Master's Thesis, University of Tennessee, 2023.
https://trace.tennessee.edu/utk_gradthes/10110
Included in
Electrical and Electronics Commons, VLSI and Circuits, Embedded and Hardware Systems Commons