Doctoral Dissertations
Date of Award
5-2020
Degree Type
Dissertation
Degree Name
Doctor of Philosophy
Major
Computer Engineering
Major Professor
Mark E. Dean
Committee Members
James S. Plank, Garrett S. Rose, Andy Sarles
Abstract
Neuromorphic computers take inspiration from the brain to perform computation in a way similar to how a brain works. They perform computation by evaluating Spiking Neural Networks (SNN) to model how the electronic pulses travel through a collection of neurons. The neurons in the network spike, or fire a pulse, once the accumulated inputs to the neuron exceed a specific threshold. Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), and other chip/multi-chip level implementations can be used to construct Dynamic Adaptive Neural Network Arrays (DANNA) and its successor DANNA2. In many use cases, the neuromorphic hardware is connected to a traditional computing system that is used to load neural network configurations, provide network input, process network output, and monitor the status of the network. To ensure robust communication, a custom, hardware-based, go-back-n, automatic repeat request protocol is presented, which allows for high-throughput, low-latency, error-free communication using the Aurora link-level protocol over the GTX/GTH high-speed serial transceivers found on Xilinx FPGAs. Multiple DANNA2 element cores are tiled into a grid array and placed within a KCU1500 Kintex Ultrascale FPGA to build a reconfigurable hardware neuromorphic processor. For resource-constrained environments, these element cores can also be densely packed onto the FPGA for a specific network, requiring fewer resources for a non-reconfigurable neuromorphic processor. For high-performance computation, multiple reconfigurable neuromorphic processors with grid arrays are tiled together with a Neuromorphic Array Communication Controller (NACC) to build a large-scale neuromorphic system called Scaled-up NACC (SNACC). SNACC uses scalable, high-performance, point-to-point connections to network the neuromorphic processors into a two-dimensional array. The neuromorphic processors are connected back to the host PC through a hierarchical, high-speed network made possible through the use of one or more NACCs. These new hardware DANNA2 neuromorphic processors are used to further research with recurrent spiking neural networks (RSNNs). Specifically, this work uses the new hardware for evolutionary optimization of neural networks using genetic algorithms, for reservoir computing, and for solving graph algorithms. Additionally, the hardware can be used for real-time processing as demonstrated with target acquisition and obstacle avoidance on a ground-roaming autonomous robot.
Recommended Citation
Young, Aaron Reed, "SNACC: The Scaled-up Neuromorphic Array Communications Controller. " PhD diss., University of Tennessee, 2020.
https://trace.tennessee.edu/utk_graddiss/5843
Comments
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