Doctoral Dissertations

Orcid ID

http://orcid.org/0000-0003-4295-9853

Date of Award

12-2019

Degree Type

Dissertation

Degree Name

Doctor of Philosophy

Major

Electrical Engineering

Major Professor

Garrett Rose

Committee Members

Nicole McFarlane, Jinyuan Sun, Hoon Hwangbo

Abstract

Security is one of the major design criteria for modern computing system. Computing systems are becoming more compact and connected day by day. Due to the large scale connectivity, various security threats are causing failure to confidentiality, integrity, availability and many other basic security criteria. On the other hand, the compact devices used in the embedded computing systems can hardly afford resource hungry security techniques. As improvements in conventional technologies has almost come to a saturation, many emerging technologies are drawing researcher's attention in this regard. This work proposes design techniques using emerging technologies in order to find more comprehensive security solutions for embedded computing system. Two major part of conventional Von-Neuman or Harvard architectures are memory and processing unit which requires individual attention for security against various threats. Chaotic oscillator based logic and RRAM based memory design are explored in this work to mitigate different existing security vulnerabilities with significantly lower overhead. Proposed design techniques are applied in a RISC-V microarchitecture to ensure memory integrity and enhance the security against unauthorized code execution and instruction reverse-engineering based on side channel power attack. Security of the proposed design techniques are found to be at the desired level while consuming a very low overhead as compared to existing mitigation techniques against the same set of vulnerabilities.

Comments

Part of this document were previously published in IEEE Transaction on VLSI, Hardware Oriented Security and Trust (HOST'17), Asian Hardware Oriented Security and Trust (AsianHOST'16), Great Lake Symposium on VLSI (GLSVLSI'19).

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