MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR

Author

Md Sakib Hasan, University of Tennessee, KnoxvilleFollow

Date of Award

8-2017

Degree Type

Dissertation

Degree Name

Doctor of Philosophy

Major

Electrical Engineering

Major Professor

Syed K. Islam

Committee Members

Benjamin J. Blalock, Nicole McFarlane, Ramakrishnan Kalyanaraman

Abstract

As the device dimensions have reduced from micrometer to nanometer range, new bulk silicon devices are now facing many undesirable effects of scaling leading device engineers to look for new process technologies. Silicon-on-insulator (SOI) has emerged as a very promising candidate for resolving the major problems plaguing the bulk silicon technology. G⁴FET [G4FET] is a SOI transistor with four independent gates. Although G⁴FET has already shown great potential in different applications, the widespread adoption of a technology in circuit design is heavily dependent upon good SPICE (Simulation Program with Integrated Circuit Emphasis) models. CAD (Computer Aided Design) tools are now ubiquitous in circuit design and a fast, robust and accurate SPICE model is absolutely necessary to transform G⁴FET into a mainstream technology.

The research goal is to develop suitable SPICE models for G⁴FET to aid circuit designers in designing innovative analog and digital circuits using this new transistor. The first phase of this work is numerical modeling of the G⁴FET where four different numerical techniques are implemented, each with its merits and demerits. The first two methods are based on multivariate Lagrange interpolation and multidimensional Bernstein polynomial. The third numerical technique is based on multivariate regression polynomial to aid modeling with dense gridded data. Another suitable alternative namely multidimensional linear and cubic spline interpolation is explored as the fourth numerical modeling approach to solve some of the problems resulting from single polynomial approximation.

The next phase of modeling involves developing a macromodel combining already existing SPICE models of MOSFET (metal–oxide–semiconductor field-effect transistor) and JFET (junction-gate field-effect transistor). This model is easy to implement in circuit simulators and provides good results compared to already demonstrated experimental works with innovative G⁴FET circuits. The final phase of this work involves the development of a physics-based compact model of G⁴FET with some empirical fitting parameters. A model for depletion-all-around operation is implemented in circuit simulator based on previous work. Another simplified model, combining MOS and JFET action, is implemented in circuit simulator to model the accumulation mode operation of G⁴FET.

Recommended Citation

Hasan, Md Sakib, "MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR. " PhD diss., University of Tennessee, 2017.
https://trace.tennessee.edu/utk_graddiss/4626