Low-Voltage Analog Circuit Design Using the Adaptively Biased Body-Driven Circuit Technique

Author

Stephen Christopher Terry, University of Tennessee - Knoxville

Date of Award

8-2005

Degree Type

Dissertation

Degree Name

Doctor of Philosophy

Major

Electrical Engineering

Major Professor

Benjamin J. Blalock

Committee Members

Syed K. Islam, Charles L. Britton, Jr., M. Nance Ericson, Vasilios Alexiades

Abstract

The scaling of MOSFET dimensions and power supply voltage, in conjunction with an increase in system- and circuit-level performance requirements, are the most important factors driving the development of new technologies and design techniques for analog and mixed-signal integrated circuits. Though scaling has been a fact of life for analog circuit designers for many years, the approaching 1-V and sub-1-V power supplies, combined with applications that have increasingly divergent technology requirements, means that the analog and mixed-signal IC designs of the future will probably look quite different from those of the past. Foremost among the challenges that analog designers will face in highly scaled technologies are low power supply voltages, which limit dynamic range and even circuit functionality, and ultra-thin gate oxides, which give rise to significant levels of gate leakage current.

The goal of this research is to develop novel analog design techniques which are commensurate with the challenges that designers will face in highly scaled CMOS technologies. To that end, a new and unique body-driven design technique called adaptive gate biasing has been developed. Adaptive gate biasing is a method for guaranteeing that MOSFETs in a body-driven simple current mirror, cascode current mirror, or regulated cascode current source are biased in saturation—independent of operating region, temperature, or supply voltage—and is an enabling technology for high-performance, low-voltage analog circuits. To prove the usefulness of the new design technique, a body-driven operational amplifier that heavily leverages adaptive gate biasing has been developed. Fabricated on a 3.3-V/0.35-μm partially depleted silicon-onv-insulator (PD-SOI) CMOS process, which has nMOS and pMOS threshold voltages of 0.65 V and 0.85 V, respectively, the body-driven amplifier displayed an open-loop gain of 88 dB, bandwidth of 9 MHz, and PSRR greater than 50 dB at 1-V power supply.

Recommended Citation

Terry, Stephen Christopher, "Low-Voltage Analog Circuit Design Using the Adaptively Biased Body-Driven Circuit Technique. " PhD diss., University of Tennessee, 2005.
https://trace.tennessee.edu/utk_graddiss/2299