Optimal clock distribution in VLSI systems

Author

P. R. Mukund

Date of Award

12-1990

Degree Type

Dissertation

Degree Name

Doctor of Philosophy

Major

Electrical Engineering

Major Professor

D. W. Bouldin

Committee Members

E. J. Kennedy, J. M. Rochelle, R. E. Bodenheimer, D. W. Straight

Abstract

Global electrical design issues such as power distribution and clock distribution in VLSI design have assumed added dimensions as feature sizes below one micron and device counts of more than a million are becoming feasible. This dissertation presents a methodology for optimally distributing the clock signal in synchronous digital VLSI circuits. Optimality is measured in terms of minimizing delay in each critical path as well as the differences in delays between different paths. The inputs to the system consist of the location of each cell, the input capacitance of each cell and the locations of all possible buffer sites. The outputs consist of the optimal number and location of buffers as well as a netlist for routing the clock signal. This system provides a formal application specific methodology for optimal clock distribution whose utility increases with the size of the circuit.

Recommended Citation

Mukund, P. R., "Optimal clock distribution in VLSI systems. " PhD diss., University of Tennessee, 1990.
https://trace.tennessee.edu/utk_graddiss/11464