Date of Award
Master of Science
Leon M. Tolbert, Daniel J. Costinett
With the benefits of fast switching speed, low on-resistance and high thermal conductivity, silicon carbide (SiC) devices are being implemented in converter designs with high efficiency and high power density. Consequently, SiC power modules are needed. However, some of the preestablished package designs for silicon based power modules are not suitable to manifest the advantages of SiC devices. Therefore, this thesis aims at optimizing the package design to utilize the fast switching capability of SiC devices.
First, the power loop parasitic inductance induced by the package can lead to large voltage spikes with the fast switching SiC device. It can potentially exceed the device’s voltage ratings and affect its safe operation.
Second, to achieve high power density design with SiC devices, the package’s cooling performance needs to be improved.
Third, to design a package for high current applications with multiple chips in parallel, a proper scaling method is needed to ensure all the devices undertake the same voltage stress in switching transients. For P-cell/N-cell designs with split scaling, a new parasitic parameter, namely, middle-point parasitic inductance Lmiddle will be introduced. Its role should be understood.
Lastly, the unbalanced dynamic switching loss can lead to different state junction temperatures among paralleled devices. Thermal coupling can help to reduce the temperature imbalance, and its role should be quantitatively investigated.
To meet the first two requirements, a new package design is proposed with reduced parasitic inductance and double-sided cooling. Compared to a baseline package, more than 60% reduction of parasitic inductance is achieved.
The middle-point parasitic inductance’s effect on device’s switching transients is analyzed in the frequency domain. Then a dedicated power module is fabricated with the capability of varying Lmiddle. Experiment results show that as Lmiddle increases, different voltage stresses are imposed on the MOSFET and anti-parallel diode.
Electrothermal simulations are implemented to investigate steady state junction temperatures of paralleled devices considering unbalanced switching losses at different thermal coupling conditions. It is observed that both devices’ junction temperatures will increase as the coupling coefficient is increased. However, the junction temperature imbalance will decrease. This is verified by the experiment result.
Yang, Fei, "Design Considerations for Paralleling Multiple Chips in SiC Power Modules. " Master's Thesis, University of Tennessee, 2017.