Date of Award

8-2017

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Daniel Costinett

Committee Members

Leon Tolbert, Syed Islam, Benjamin Blalock

Abstract

Battery charging circuits for mobile applications, such as smart phones and tablets, require both small area and low losses. In addition, to reduce the charging time, high current is needed through the converter. In this work, exploration of the Buck, the 3-Level Buck and the Hybrid Buck converter is performed over the input voltage, the total FET area and the load current. An analytical loss model for each topology is constructed and constrated by experimental results. In addition, packaging and bond wire impact on on-chip losses is analyzed by 3D modeling. Finally, a comparison between the topologies is presented determining potential candidates for a maximum on-chip loss of 2 W at output voltage of 4 V and 10 A of output current.

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