Date of Award
Master of Science
Benjamin J. Blalock
Syed K. Islam, M. Nance Ericson
This thesis presents the design and implementation of a CMOS shaper with baseline restoration for use in the silicon-based neutron detector front-end to be used at the Spallation Neutron Source (SNS) at the Oak Ridge National Laboratory (ORNL). The system consists of a voltage-to-current (V-to-I) converter, a four-pole complex-conjugate semi-Gaussian current-input active filter, and a ground-sensing baseline restorer (BLR) operational transconductance amplifier (OTA). The first prototype chip Patara has been fabricated in the TSMC 0.35-micron process, and experimental results show that proper functionality was achieved. The shaper, which is influenced by a real pole prior to the V-to-I converter, has poles at approximately 2 MHz and approximates a Gaussian output shape for an input pulse with rise time near 20 nanoseconds. The output signal has a full-width half-maximum (FWHM) of around 270 nanoseconds and a settling time of 0.6 microseconds, allowing for a 1- microsecond pulse-pair resolution. The shaper and baseline restorer have selectable polarity to accommodate input pulses of both polarities.
Britton, Jonathan Lanier, "Design and Implementation of a Complex-conjugate Shaper and Baseline Restorer for a Silicon-based Neutron Detector Front-end. " Master's Thesis, University of Tennessee, 2006.