A PLL frequency synthesizer and Gilbert cell multiplier for a 916 MHz ISM band transmitter realized in 0.5 [mu]m [i.e. micrometer] CMOS technology

This thesis is a study of the design of a 3^rd order phase lock loop (PLL) and Gilbert cell multiplier to implement a 916MHz ISM band transmitter in 0.5μm CMOS technology. The transmitter is designed for implementing distributed biosensor systems for environmental monitoring.

The transmitter is described from a system level with the discussion of design issues concerning system topology and communication signal requirements as related to project requirements. The PLL system is described as a negative feedback system and important design considerations are discussed. Each PLL and transmitter system component is analyzed and discussed. A prototyped double balanced Gilbert cell multiplier with a power gain of 8dB, -10dBm compression point, and dissipates 7.2mW of power is analyzed and presentedThe analysis and design of a prototyped current mode logic frequency divider with a fixed division factor of 256 is presented. The frequency divider dissipated 15mW of power for a -20dBm 916 MHz input signal with a maximum operating frequency of 1.8 GHz. An off-chip LC tank voltage controlled oscillator was prototyped with a tuning range of 120 MHz, dissipated 3.3mW, -15dBm single-ended output signal, and had a phase noise performance of -60dBc at a 10 kHz offset and -80dBc at 100 kHz offset is analyzed and presentedThe design and simulation issues of a digital phase frequency detector (PFD), charge pump, and loop filter is presented. The charge pump was designed to source or sink a 10 μA current for an output voltage to within 0.1 V of the power supply voltages. Results show that the final transmitter can be successfully implemented with the prototyped and simulated transmitter components.