A VLSI implementation of Jansson's iterative deconvolution algorithm

This thesis will present a Very Large Scale Integration (VLSI), Digital Signal Processing (DSP) chip that will significantly improve the processing throughput for Jansson's iterative deconvolution algorithm. The chip will enable Jansson's algorithm to be used for real-time DSP applications which formerly due to speed limitations were not possible. This will enable researchers to take further advantage of the features unique to iterative deconvolution. The chip will process 8-bit, 2's complement input data at a 520.625 KHz sample rate to produce 8-bit results. The deconvolution is computed using a 32-point coefficient vector. The convolution is carried out by a time multiplexed, finite impulse response (FIR) filter array. All processing is done in a bit-parallel, pipelined fashion. The chip layout was accomplished using a high level hardware description language called SDL which is part of the Lager IV software package. This design approach produced a parameterized chip description,allowing future design changes or improvements to be made rapidly without neccesitating a complete redesign effort.