Design and synthesis of an Intel 80C51 compatible microprocessor optimized for reduced instruction time (RIT) execution

The purpose of this research was to explore the feasibility and design of a Reduced Instruction Time (RIT) version of the present Intel 80C51 family of microprocessors. A new architecture was developed to attain a processor that has either high performance or low power dissipation by using fewer clock cycles to execute an instruction, dual-edge triggered flip-flops, selective clocking of components, and a hardware-oriented structure instead of the bidirectional busing scheme used by Intel. For this project, the major goal was to implement a microprocessor that is object-code compatible with the Intel 80C51, but the instructions are implemented in a minimum number of clock cycles. The RIT processor should execute instructions between 4.8 to 48 times faster than the Intel 80C51 microprocessor with an average improvement factor of 9.5 over the Intel processor in terms of the number of clock cycles used to implement an instruction. At its maximum execution rate, the RIT processor should have a higher throughput than any member of the Intel 80C51 microprocessor family presently on the market. The implementation of this design is specified using a hardware description language that generates a standard cell layout from a behavioral description. With a layout generated from the code, this design should be very efficient with a long living potential. In addition, the modular design approach and hierarchical control structure should produce a core processor that executes all instruction of the Intel 80C51 microprocessor and a basic interrupt structure capable of incorporating additional components (timers, serial communications, etc) into the core processor.