Development of a multiplicity discriminator for high energy physics experiments

A current output multiplicity discriminator for use in the front-end electronics (FEE) of the Multiplicity Vertex Detector (MVD) for the PHENIX detector at RHIC has been developed in the Orbit Semiconductor 1.2 µ CMOS, n-well process. Requirements for the multiplicity discriminator include low-power, small area, high speed and common threshold matching. Additionally the discriminator must trigger on input signals ranging from 0.25 MIP(20 mV for the detector) to 5 MIP. Frequency response of the discriminator is such that the circuit is capable of generating an output for every detector beam crossing (105 ns). One channel of multiplicity discriminator occupies an area of 85 µ by 530 µ and consumes 515 µW. Details of the design and results from prototype device testing are presented.