Development of an FPGA-based heap manager for the PHENIX multiplicity vertex detector

In this thesis, a technique for implementation of a heap manager for management and control of instrumentation for the PHENIX Multiplicity Vertex Detector (MVD) is discussed. In the PHENIX MVD, an analog memory is utilized as an analog storage device so that analog data may be acquired from a charge-sensitive preamp, examined, and, if an event threshold is realized, converted by an analog-to-digital converter into digital data. A field programmable gate array (FPGA) solution for control and data management is developed as a means of maintaining the front-end electronics, which includes preamps, analog memories, and ADCs as well as a number of support logic devices. The heap manager, as a system controller, provides all timing and digital data acquisition functions needed by the MVD system; and a series of interfaces contained in the heap manager provides the link between an external CPU and the front-end electronics. Results from a prototype of the MVD system are examined and used to expose the strengths and weaknesses of the heap manager; and further refinement of the heap manager architecture is enacted to take advantage of the knowledge gleaned from the prototype and yields the power, speed, and resource allocation specifications for the system as configured for implementation in a multi-chip module. The heap manager is shown to be fully functional with a clock of 60 MHz and has a power dissipation of approximately 700 mW at 40 MHz.