A methodology for designing parallel/pipelined systems

Serial processing inherently limits the speed at which a given function can be per- formed. By processing various parts of the function in parallel, the performance can be improved, but at a price higher design effort. Serial processing lends itself to de- sign methodologies which are very mature, whereas design methodologies for parallel processing are less developed. By pipelining the parallel processing, the performance is again increased, but at an even higher price design methodologies are even less developed.

This dissertation presents a methodology for designing parallel/pipelined systems based on the design of three systems (two hardware and one software). The methodology assumes that the designer has previous digital design experience and wishes to expand the range of possible designs to include parallel/pipelined implementations. The hard- ware designs are Application Specific Integrated Circuit (ASIC) designs implemented in CMOS gate arrays. The software design is implemented on an i860 based multiproces- sor system. Various architectures for the designs and the corresponding trade-offs are presented including ones which were considered but not used. An emphasis is placed on the application of the methodology to ASIC development, but the broader application to other areas is also presented.