Masters Theses
Date of Award
5-2011
Degree Type
Thesis
Degree Name
Master of Science
Major
Electrical Engineering
Major Professor
Benjamin J. Blalock
Committee Members
Charles Britton, Jeremy Holleman
Abstract
A pulse-width locked loop (PWLL) circuit is reported that compensates for process, voltage, and temperature (PVT) variations of a linear ramp generator within a 12-bit multi-channel Wilkinson (single-slope integrating) Analog-to-Digital (ADC). This PWLL was designed and fabricated in a 0.5-um Silicon Germanium (SiGe) BiCMOS process. The PWLL architecture that is comprised of a phase detector, a charge-pump, and a pulse width modulator (PWM), is discussed along with the design details of the primary blocks. Simulation and silicon measurement data are shown that demonstrate a large improvement in the accuracy of the PVT-compensated ADC over the uncompensated ADC.
Recommended Citation
Tham, Kevin Vun Kiat, "PVT Compensation for Single-Slope Measurement Systems. " Master's Thesis, University of Tennessee, 2011.
https://trace.tennessee.edu/utk_gradthes/915