Masters Theses

Date of Award

8-2004

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Dr. Donald W. Bouldin

Committee Members

Dr. Gregory D. Peterson, Dr. Chandra Tan

Abstract

Designs are becoming bigger in size, faster in speed and larger in complexity with the emergence of System-on-Chip designs. Hardware components and embedded software co-exist in such designs making it necessary to describe designs at higher levels of abstraction. Describing designs at higher levels of abstraction enables faster simulation, hardware software co-simulation and architectural exploration. SystemC is a solution.

Also the time to market can be reduced greatly if previously designed intellectually property (IP) described in a hardware description language (HDL) can be reused in SystemC.

In this research SystemC modules were successfully developed and verified from Verilog using existing tools. Verilator is a tool that translates synthesizable Verilog into C++ or SystemC code with certain limitations. The generated SystemC code was simulated and compared against the simulation results of the original Verilog code. To add credibility several simple and a few large cores were transformed into SystemC and the simulation results of the Verilog and the SystemC code were compared.

Pure SystemC code was synthesized using Synopsys’ SystemC Compiler and DC Shell and an area report based on the TSMC 0.18 technology was generated. The synthesis produced a Verilog code, which was simulated, and the simulations compared to the SystemC simulations

Available VHDL to Verilog and vice-versa conversion tools were also investigated. Mentor Graphics’ HDL Designer and Ocean Logic’s VHDL to Verilog converter were used for this purpose. Simulation results before and after the conversions were compared.

Download
Files over 3MB may be slow to open. For best results, right-click and select "save as..."

Share

COinS