Masters Theses

Date of Award

12-2005

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Don Bouldin

Committee Members

Gregory Peterson, Syed Islam

Abstract

In this project, we designed and implemented a System-on-Chip platform with embedded test structures. The baseline platform consists of a Leon2 CPU, AMBA on-chip bus, and an Advanced Encryption Standard decryption module. Reconfigurable test logic blocks were embedded to form the test structure that can be used in post-silicon debug and verification.

The System-on-Chip platform was designed at the register transistor level and implemented in an 180nm CMOS process. Test logic instrumentation was done with DAFCA, Inc. (Design Automation for Flexible Chip Architecture) pre-silicon tools. The design was then synthesized using the Synopsys Design Compiler and placed and routed using Cadence SOC Encounter. Total transistor count is about 2 million, including 800K transistors for original platform and 700K for debugging module serving as on chip logic analyzer. Core size of the design is 3mm x 3mm and the system is working at 15MHz. Design verification was done with Mentor Graphics ModelSim and Cadence NCSim. Simulations were also used with the post-silicon environment to verify the functionality of the embedded test structure.

With a baseline platform ready and verified, designers can obtain high quality derivative designs quickly and easily. The visibility and the controllability of internal signals can greatly accelerate the testing and debug process, while the ability of post-silicon logic fixing can be used to verify design patch and enhance the reliability of the design. The whole design flow is cost effective in multi-million-transistor design because re-spins and delays in bringing a product to market may be avoided.

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