Verification of Intellectual Property Blocks Using Reconfigurable Hardware

Author

Koay Teng Kuan, University of Tennessee - Knoxville

Date of Award

12-2002

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Donald W. Bouldin

Committee Members

Gregory Peterson, Michael Langston

Abstract

The purpose of this thesis is to develop a procedure to verify intellectual property (IP)cores on the Pilchard platform which contains reconfigurable hardware. The hardware and tools used for the verification process are documented.

Two IP cores are used as examples of how the Pilchard design flow is to be applied. One core that does a simple logical function is implemented to serve as a demonstration of Pilchard read and write operations. To demonstrate the versatility of the hardware platform, a complex core that performs a Fast Fourier Transform operation was also implemented successfully.

Results from these IP implementations indicate that for high performance IP cores to be verified on the Pilchard, careful attention must be exercised to minimize the possible timing delay that occurs during place-and-route.

Recommended Citation

Kuan, Koay Teng, "Verification of Intellectual Property Blocks Using Reconfigurable Hardware. " Master's Thesis, University of Tennessee, 2002.
https://trace.tennessee.edu/utk_gradthes/2082