Masters Theses

Date of Award

8-2006

Degree Type

Thesis

Degree Name

Master of Science

Major

Electrical Engineering

Major Professor

Donald Bouldin

Committee Members

Syed Islam, Gregory Peterson

Abstract

Hardware design in VHDL can be a tedious and daunting task. One of the final steps is to realize the design in hardware. Whether targeting a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), some time needs to be spent optimizing the design to meet project requirements. This paper details the use of the Synplicity physical synthesis toolsets for FPGAs on the UT Solaris workstation cluster, evaluation of the Synplicity physical synthesis toolsets to determine their efficacy in achieving multiple solutions over the power-delay-area design space and evaluation of the Liberator toolset for ASIC design to determine its efficacy in achieving multiple solutions over the power-delay-area design space.

Walkthrough tutorials were created to assist users in becoming familiar with using Synplify and Amplify. An automation script was run with Synplify Pro on a VHDL implementation of AES targeting a Xilinx Virtex-II Pro (XC2VP30-6). Synplify generated solutions varying from 74.7MHz to 112.8MHz with an area utilization of 44% to 45%. Liberator invoked the design space search algorithm (DSSA) developed by Fuat Karakaya against each of five circuits. The DSSA was stopped after generating 32 points for the 32-bit adder, 32-bit multiplier, 32-bit complex multiplier and the 32-bit FIR filter. The 64-bit FFT stopped after 14 days of run time. The power-delay-area product (PDAP) ranged from 1.85 to 4.3 µJ*µm2 for the adder, 1.9 to 3.4 µJ*µm2 for the multiplier, 39.6 to 90.5 µJ*µm2 for the complex multiplier, 23 to 33.6 µJ*µm2 for the FIR and 91.8 to 133.7 µJ*µm2 for the FFT.

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