Doctoral Dissertations

Surin Khomfoi

Date of Award

5-2007

Degree Type

Dissertation

Degree Name

Doctor of Philosophy

Major

Electrical Engineering

Major Professor

Leon M. Tolbert

Committee Members

Jack S. Lawler, J. Wesley Hines, Fangxing Li

Abstract

A fault diagnostic and reconfiguration system in a multilevel inverter drive (MLID) using artificial intelligent based techniques is developed in this dissertation. Output phase voltages of a MLID can be used as valuable information to diagnose faults and their locations. It is difficult to diagnose a MLID system using a mathematical model because MLID systems consist of many switching devices and their system complexity has a nonlinear factor. Therefore, a neural network (NN) classification is applied to the fault diagnosis of a MLID system. Multilayer perceptron (MLP) networks are used to identify the type and location of occurring faults. The principal component analysis (PCA) is utilized in the feature extraction process to reduce the NN input size. A lower dimensional input space will also usually reduce the time necessary to train a NN, and the reduced noise may improve the mapping performance. The genetic algorithm is also applied to select the valuable principal components. The comparison among MLP neural network (NN), principal component neural network (PC-NN), and genetic algorithm based selective principal component neural network (PC-GA-NN) are performed.

Proposed neural networks are evaluated with simulation test set and experimental test set. The PC-NN has improved overall classification performance from NN by about 5% points, whereas PC-GA-NN has better overall classification performance from NN by about 7.5% points. Therefore, the application of a genetic algorithm improves the classification from PC-NN by about 2.5% point. The overall classification performance of the proposed networks is more than 90%.

A reconfiguration technique is also developed. The effects of using the developed reconfiguration technique at high modulation index are addressed. The developed fault diagnostic system is validated with experimental results. The developed fault diagnostic system requires about 6 cycles at 60 Hz to clear an open circuit and about 9 cycles at 60 Hz to clear a short circuit fault. The experimental results show that the developed system performs satisfactorily to detect the fault type, fault location, and reconfiguration.

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