Date of Award
Master of Science
L. Montgomery Smith, Roy S. Joseph
Digital design engineers often must balance the design issues of implementing finite state machines in field programmable logic devices, obtaining the highest clock frequency possible, and keeping the amount of logic resources utilized as small as possible. This and other design issues are discussed in this thesis. A comparison of VHDL and microprogrammed implementations of synchronous finite state machines in field programmable logic devices is presented. Three representative state machines, a Tap controller, temperature controller, and quarter-inch tape cartridge controller, with 16, 22, and 61 states respectively were chosen to be implemented using five basic methods: VHDL, a scaled-down microsequencer utilizing embedded array blocks (EABs) as the memory storage element, a scaled-down microsequencer utilizing lookup tables (LUTs) as the memory storage element, and a full-scale microsequencer with EABs and a full-scale microsequencer with LUTs. Altera Max Plus II software was used including versions 7.21 and 9.4. The Altera Flex 10K and 10KE components were used. The results from these methods were analyzed and compared. Areas of interest were clock frequency, logic cell utilization, and software efficiency As the number of states was increased for a finite state machine, VHDL became increasingly inefficient in terms of clock frequency and resource utilization. A scaled-down microsequencer approach using LUTs as the memory storage element was found to be the most efficient in overall clock frequency and resource utilization.
Hardcastle, Michael L., "A comparison of VHDL and microprogrammed implementations of synchronous finite state machines in field programmable logic devices. " Master's Thesis, University of Tennessee, 2000.