Date of Award
Master of Science
Donald W. Bouldin
Hamar Elhanany, Gregory D. Peterson, Mark A. Buckner
iii Abstract The goal to this research was to develop a scheme to optimize a digital filter design using an optimization engine and hardware-accelerated simulation using a Field Programmable Gate Array (FPGA). A parameterizable generic digital filter, which was fully implemented on a prototyping board with a Xilinx Virtex-II Pro xc2vp30-7-ff896 FPGA, was developed using Xilinx System Generator for DSP. The optimization engine, which actually is a random candidate generator that will eventually be replaced by a differential evolution engine, was implemented using MATLAB along with a candidate evaluator and other supporting programs. Automatic hardware co-simulations of 100 candidate filters were performed successfully to demonstrate that this approach is feasible, reliable and efficient for complex systems.
Liang, Getao, "Optimization of Digital Filter Design Using Hardware Accelerated Simulation. " Master's Thesis, University of Tennessee, 2007.