Date of Award
Master of Science
Materials Science and Engineering
David C. Joy
Philip D. Rack, Michael L. Simpson
As we approach the 65nm technological node, transistor gates with dimensions of the order of 40nm are being manufactured. As the device performance is directly related to the dimensions of the gate, critical dimension (CD) control becomes an important part of the fabrication process. Characterization of these small feature size, generally referred to as Metrology, is an indispensable ingredient of the semiconductor manufacturing processes. Metrology relies not only on the precision, but also the accuracy of commercially used metrology tools like the CD-SEM. To facilitate the magnification calibration of the CD-SEM, an easy access to standard reference artifact traceable to international specifications is an added advantage. Considerable literature is available for CD-SEM, which relies on in-house artifacts or general test objects. The absence of commercially available artifacts hinders evaluation of different CD-SEM. The objective of this abstract is to introduce the fabrication and characterization of artifacts for the sub-100nm metrology, which can be made available in wafer form at low cost.
In this work, artifacts have been designed and fabricated for precise magnification calibration of the CD-SEM. The designing of the artifacts takes into account the proximity effect, a problem associated with the e-beam exposure, to produce dense grid type structure in the sub-100nm region. The structures are fabricated using the e-beam lithography tool, operated at 50KeV. The artifacts have been fabricated on a thin layer of negative resist HSQ spun on silicon substrate. Subsequent development in 0.26N TMAH gives a structure on silicon wafer, thereby eliminating contamination issues.
Furthermore, characterization of the artifacts for line pitch determination is carried out using “Measure” (Spectel Corp.), which provides an absolute calibration of the image pixel size that can then be used to measure other features. The low values for the line edge roughness (LER) further facilitate precise linewidth metrology.>/p>
Deo, Sachin Jayant, "Traceable Standard for Sub - 100nm Metrology. " Master's Thesis, University of Tennessee, 2007.