Masters Theses

Date of Award

12-2006

Degree Type

Thesis

Degree Name

Master of Science

Major

Computer Engineering

Major Professor

Gregory D. Peterson

Committee Members

Donald W. Bouldin, Robert J. Harrison

Abstract

To help promote more widespread adoption of hardware acceleration in parallel scientific computing, we present portable, flexible design components for pseudorandom number generation. Due to the success of the Scalable Parallel Random Number Generators (SPRNG) software library in stochastic computations (e.g., Monte Carlo simulations), we developed an efficient and portable hardware architecture fully compatible with SPRNG’s Parallel Additive Lagged Fibonacci Generator (PALFG). Our general design produces identical results for all the parameter sets that SPRNG supports and yields high performance parallel random number generators which can each generate 162 million 31-bit uniform random integers per second on Xilinx Virtex II Pro FPGAs. The friendly design interface makes it easy for users to integrate into their applications, particularly computational scientists unfamiliar with reconfigurable hardware. Due to its fast generation speed and friendly interface, this uniform random number generator is being targeted as an open core for parallel scientific computing.

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