Doctoral Dissertations

Date of Award

8-2018

Degree Type

Dissertation

Degree Name

Doctor of Philosophy

Major

Electrical Engineering

Major Professor

Syed K. Islam

Committee Members

Aly E. Fathy, Mohamed R. Mahfouz, Nicole McFarlane

Abstract

Technological enhancements in a low-power CMOS process have promoted enhancement of advanced circuit design techniques for sensor related electronic circuits such as wearable and implantable sensor systems as well as wireless sensor nodes (WSNs). In these systems, the powering up the electronic circuits has remained as a major problem because battery technologies are not closely following the technological improvements in semiconductor devices and processes thus limiting the number of sensor electronics modules that can be incorporated in the design of the system. In addition, the traditional batteries can leak which can cause serious health hazards to the patients especially when using implantable sensors. As an alternative solution to prolonging the life of battery or to mitigate serious health problems that can be caused by battery, energy harvesting technique has appeared to be one of the possible solutions to supply power to the sensor electronics. As a result, this technique has been widely studied and researched in recent years. In a conventional sensor system, the accessible space for batteries is limited, which restricts the battery capacity. Therefore, energy harvesting has become an attractive solution for powering the sensor electronics. Power can be scavenged from ambient energy sources such as electromagnetic signal, wind, solar, mechanical vibration, radio frequency (RF), and thermal energy etc. Among these common ambient sources, RF and piezoelectric vibration-based energy scavenging systems have received a great deal of attention because of their ability to be integrated with sensor electronics modules and their moderate available power density. In this research, both RF and piezoelectric vibration-based energy harvesting systems have been studied and implemented in 130 nm standard CMOS process.

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