Date of Award


Degree Type


Degree Name

Doctor of Philosophy


Electrical Engineering

Major Professor

Syed Kamrul Islam

Committee Members

Benjamin J. Blalock, Leon M. Tolbert, Philip D. Rack


This thesis presents the work on analytical modeling and simulation of a silicon carbide (SiC) power MOSFET, model verification with test data, and device characterization and parameter extraction of the SPICE model. The development of temperature models for a lateral as well as a vertical MOSFET in SiC are also presented.

The model takes into account the various short channel effects in the DIMOS channel region as well as the velocity saturation effect in the drift region. Considering the SiC material processing limitations and feedback from the system level application group, an application specific SiC power MOSFET structure has been proposed. The device dimensions were chosen to obtain the desired specific on-resistance and breakdown voltage of the power MOSFET. A good agreement between the analytical model and the MEDICI simulation is demonstrated.

The temperature models include the effects of temperature on the threshold voltage, carrier mobility, the body leakage current, and the drain and source contact region resistances for a lateral MOSFET and the effects of temperature on the threshold voltage, carrier mobility, the body leakage current, drift region resistance and channel resistance for a vertical MOSFET. The temperature dependent compensating current elements are introduced in the model. These compensating currents contribute to the total current at high temperatures.

A rigorous testing and characterization has been carried out on a 4H-SiC DIMOS transistor test device. SPICE parameters have been extracted from the measurements and a SPICE model for the DIMOS transistor has been developed. The models developed in this research will not only help the SiC device researchers in the device behavioral study but will also provide a SPICE model for circuit designers.

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